Ensure that all FPGA designs are developed in accordance with the company design process.
Detailed RTL design in VHDL.
Support integration of the FPGA into the target hardware.
Gate level implementation of the design including synthesis, placement and static timing analysis.
Verification of RTL design and documenting the verification that was performed.
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Progressive Recruitment, a trading division of SThree Partnership LLP is acting as an Employment Business in relation to this vacancy | Registered office | 1st Floor, 75 King William Street, London, EC4N 7BE, United Kingdom | Partnership Number | OC387148 England and Wales