5-10 years' experience in industry working on a variety of verification projects.
- Extensive knowledge of verification methodologies particularly UVM and SystemVerilog.
- Strong experience in the specification and implementation of verification infrastructures, test benches, models, assertions and functional tests in Verilog and SystemVerilog.
- Familiarity with constrained random verification methodologies, code coverage analysis and running regression tests.
- Strong VHDL/Verilog RTL Knowledge.
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Progressive Recruitment, a trading division of SThree Partnership LLP is acting as an Employment Business in relation to this vacancy | Registered office | 1st Floor, 75 King William Street, London, EC4N 7BE, United Kingdom | Partnership Number | OC387148 England and Wales