ASIC Design for Test(DFT) lead engineer with 9+ years of experience including:
Excellent knowledge of the latest state-of-the-art elements in DFT and Test.
Hands-on design experience in DFT insertion and verification of Scan/ATPG, MemoryBist and Jtag protocols using commercial test generation tools for large complex designs.
Tool set includes : VCS, Design Compiler, Spyglass, TetraMax, SMS, BSD Compiler. Cross-Clock Domain Crossing, Primetime.
Previous experience leading a team and driving technical execution results.
Experience with DFT silicon sign-off for tape out.
Verification skills include Verilog, UVM, Logic Equivalency checking and validating the test-timing of the design.
Experience working with Gate level simulation and debug with VCS and other simulators.
Post-silicon validation and debug experience including feature validation, characterization and yield analysis.
Strong verbal communication skills and ability to thrive in a dynamic environment.
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